The present invention relates to a circuit for reading the information stored in ROM and EPROM type memories according to a differential sensing mode and, in particular to an improved circuit for generating an offsetting current for discriminating between the currents which flow through a certain cell of the memory array which has been selectively addressed for reading and a virgin reference cell, according to a current offset sensing mode.
Among semiconductor nonvolatile memories, EPROM memories represent one of the most advanced field of integration in silicon. Starting from nowadays common 1 megabit devices, new devices with a capacity of up to 4 megabit have been presented lately and new ambitious goals are announced.
Together with an ever increasing packing density, the memory market requires improved performances in terms of access time, write time and power consumption. The reduction of the size of the devices poses serious problems to the achievement of these aims. In particular, the access time during a reading phase is penalized by a consequent reduction of the actual current through the memory cell and an increased influence of parasitic electric factors of the integrated structure of the cells. For these reasons, the circuits used for reading the information stored in the cells must possess an enhanced precision and reliability.
The article entitled "L'amplificatore di Lettura nei Dispositivi di Memoria EPROM" by G. Compardo, M. Dallabora and D. Novosel, published on the journal "Alta Frequenza" Vol. LVII--No. 6--July-August 1988, contains a comprehensive review of the different sense circuits which are commonly used. The relevant content of this article is intended to be incorporated herein by express reference thereto.
Basically, the architecture of a differential type sense circuit are by far more precise and less sensitive to the effects of "process spread", temperature and supply voltage variations, by treating them essentially as common mode contributions. On the other hand, there are two differential sense systems: a load-offset type and a current-offset type. A load-offset (or load-unbalance) type sense circuit and the relative operating characteristics are reproduced in FIGS. 1 and 2, respectively. The reading system is based, as it is well known, upon the unbalancing of the load transistors, respectively of the "array cell" side and of the "reference cell" side (where the reference cell is commonly constituted by a virgin memory cell), by making larger than unity the dimensional ratio between the two load transistors.
The unbalancing of the loads permits the reading of a virgin cell by introducing an element of asymmetry between the two branches of the differential sense circuit. In the diagram of FIG. 2, the respective characteristics of a virgin cell (I.sub.on) and of a written cell (I.sub.off) and of the reference current (I.sub.ref) are all shown on a single diagram purposely.
In this type of sense circuit, the reference current I.sub.ref varies with the varying of the supply voltage VCC which is applied to the control gate of the reference cell. The minimum working voltage VCC.sub.min is in this case limited by the threshold of a virgin cell V.sub.th, while the maximum operating voltage VCC.sub.max is given by the equality between I.sub.ref and I.sub.off.
Clearly the system has limitations, in static terms, toward the value of VCC.sub.max and this constitutes a drawback. A further drawback may be identified by the necessity of forming transistors having different geometrical dimensions among each other and by the necessity of employing a relatively complex sense circuit.
A typical circuit diagram and relative characteristics of a sensing system operating in a current-offset mode, are shown in FIGS. 3 and 4, respectively. According to this known alternative approach, the operating range in terms of voltage VCC is widened by modifying the reference current I.sub.ref characteristic. In the relative circuit diagram, as it may be observed in FIG. 3, the load transistors have similar dimensions. The element of asymmetry which is necessary for discriminating the sensing of a virgin cell, is provided by means of a constant current I.sub.offset which is purposely added in parallel to the cell current of the array side.
In this way, the electrical characteristics of the cells are caused to be parallel to the characteristic of the reference current. The remarkable result is that the VCC.sub.max value tends theorethically to infinity for all the cells which have undergone a threshold shift (.delta.V.sub.th) larger than the value of said additional constant current (I.sub.offset) divided by the current gain of the cell: i.e. ##EQU1##
As described in the above mentioned article, in order to improve discrimination at the limit VCC.sub.min, the contribution of the offset current is added singly on the reference side and doubled on the array side. This is schematically shown in FIG. 3 by the "two generators": I.sub.offset and I.sub.offset /2, which determine the respective offset currents through the two branches of the input circuit of the differential sense amplifier A. In this way, the three characteristics: I.sub.on, I.sub.ref and I.sub.off, of the operating diagram of FIG. 4, are always kept separated for: EQU VCC&gt;V.sub.th =VCC.sub.min
There is however another order of considerations on sense circuits concerning their dynamic characteristics. In other words, the static characteristics discussed above, define the correct margin of operation, that is of correct interpretation of the data stored in an array cell, in function of the supply voltage and therefore they offer a measure of the width of the operating range of the sense circuits toward VCC, in the hypotesis that all transients, such as the precharging of the column lines (BITLINES), the signal propagation along the relative row of the array and so forth have terminated.
Vicerversa, the dynamic characteristics have a relevance on the currents passing in the two branches of the input circuit of the differential sense amplifier during a typical reading phase, during which the actual supply voltage of the device is set, thus providing for an evaluation of the correct operation margin during a transient. These dynamic characteristics are indicative of how small will be the access time of the memory, because the response of the sense circuits will be correct only from the moment in which the current of the reference side is smaller than the current of the array side when reading a conducting cell (ON-programmed cell), and viceversa, when reading a nonconducting cell (OFFprogrammed cell).
Moreover, this latter consideration is fundamental for recognizing an intrinsic limit of a current-offset type sense circuit.
In fact, while for the case of a load-unbalance system, the current in the two branches (reference side and array side) of the sense circuit are intrinsically different for any value of the gate voltage of the cells (and therefore the circuit provides a correct sensing during a transient), in the case of a current-offset sense circuit, because the circuit is powered at VCC, there is not a transient phase for the value of the current set by the offsetting circuit and therefore, when an OFF-programmed cell must be read, the sense circuit initially provides an erroneous response because the reference side current, for a low value of the voltage applied to the gate of the array cell and of the reference cell, is lower than the current of the array side, which current represents the sum of the offsetting current, which is intrinsically constant, and of the current of the OFF-programmed cell, which is practically nil.
Only when the voltage on the gate of the reference cell whose value depends from the propagation of the signal through the array's row, becomes sufficient to generate a current through the cell greater than the offsetting current, a correct response is obtained from the circuit. This limitation at transients negatively affects the access time in comparison to the case where a load-unbalance sense circuit is used, which, on the other hand, has the disadvantage of providing a reduced operating voltage range, as seen before.